By Bang-Sup Song (auth.), Arthur H. M. Roermund, Herman Casier, Michiel Steyaert (eds.)
Analog Circuit Design includes the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit layout. every one half discusses a selected to-date subject on new and worthy layout rules within the sector of analog circuit layout. each one half is gifted by means of six specialists in that box and state-of-the-art info is shared and overviewed. This ebook is quantity 18 during this winning sequence of Analog Circuit layout, offering useful details and perfect overviews of
- shrewdpermanent information Converters,
chaired by means of Prof. Arthur van Roermund, Eindhoven collage of know-how
- Filters on Chip,
chaired by way of Herman Casier, AMI Semiconductor Fellow
- Multimode Transmitters,
chaired by way of Prof. Michiel Steyaert, Catholic collage Leuven
Analog Circuit layout is a vital reference resource for analog circuit designers and researchers wishing to maintain abreast with the newest improvement within the box. the educational insurance additionally makes it appropriate to be used in a sophisticated layout course.
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Additional info for Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters
Hence DAC errors result in a different number of missing codes at every MSB transition, yielding substantial harmonic distortion. The common analog technique to minimize DAC errors is to use large capacitors. However as discussed in Sect. 1, this comes at the cost of increased power, and due to technology limitations capacitor mismatch cannot be made arbitrarily small. 3 Digital Calibration Techniques As the outputs of ADCs are ultimately digital, rather than correcting the nonidealities of pipelined ADCs in the analog domain, the non-idealities can be corrected by manipulating the digital output of the ADC as shown in Fig.
6) where VGT D VGS VT is the overdrive voltage of the input pair’s transistors. The HD3 due to the output resistance is also proportional to Vsig squared. Assuming Eq. NT N 5/=2 Vsig =VGT . For example consider NT D 14; N D 4; Vsig D 1 V and VGT D 0:2 V, then AOL > 29 dB. Thus, for very low opamp gains, also the third-order gain error needs to be digitally calibrated with a foreground or background  routine. 3 Range-Scaling in the First Pipeline Stage The noise performance of nm-CMOS pipeline ADCs is compromised by signal swing limitations due to the low supply voltage.
The third-order harmonic distortion is at 82 dBc and all other spurious tones are below 90 dBc. The dynamic performance versus sampling rate is shown in Fig. 3 MHz input frequency. The SNR is higher than 73 dB up to a 120 MS/s 56 H. Van de Vel 95 SFDR SNR SNDR 90 85 [dB] 80 75 70 65 fs = 100 MS/s 60 0 20 40 60 80 Input frequency [MHz] 100 120 Fig. 12 Dynamic performance versus input frequency sampling rate, and the SFDR remains higher than 81 dB up to a 110 MS/s sampling rate. The dip in SFDR at 80 MS/s is attributed to a test-board issue.
Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters by Bang-Sup Song (auth.), Arthur H. M. Roermund, Herman Casier, Michiel Steyaert (eds.)